A FULLY DIFFERENTIAL HIGH-SPEED LOW VOLTAGE DOUBLE-EDGE TRIGGERED FLIP-FLOP ( DETFF ) | Semantic Scholar
An improved current mode logic latch for high‐speed applications - Kumawat - 2020 - International Journal of Communication Systems - Wiley Online Library
An active inductor employed CML latch for high speed integrated circuits | SpringerLink
Schematic timing diagram of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
A Novel Ultra High-Speed Flip-Flop-Based Frequency Divider
4-bit Counter Using High-Speed Low-Voltage CML D-Flipflops | Semantic Scholar
A Novel Ultra High-Speed Flip-Flop-Based Frequency Divider
Circuit configuration of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
Performance evaluation of the low-voltage CML D-latch topology - ScienceDirect
High Speed Digital Blocks
Low Power Rail to Rail D Flip-Flop Using Current Mode Logic Structure